TakeMS TMS1GB264C081-804 Datový list stáhnout pdf

takeMS TMS1GB264C08x-805xx

Features

240-pin Unbuffered DDR2 SDRAM

JEDEC standard 1.8V I/O (SSTL_18-compatible)

Auto Refresh (CBR) and Self Refresh Mode

Off-Chip Driver (OCD) Impedance Adjustment

On-Die Termination (ODT) supports termination values of 50, 75, and 150 ohms

Serial Presence Detect (SPD) with EEPROM

Module layout is based on JEDEC standard routing guidelines

Impedance controlled 6-layer PCB Technology

JEDEC standard form factor (133.35 mm x 30.0 mm)

DQS edge-aligned with data for READs

DQS center-aligned with data for WRITEs

Operating Temperature 0°C ~ 75°C

Description

These Memory devices are JEDEC standard unbuffered DIMM modules,

based on CMOS DDR2 SDRAM technology.

These devices consist of CMOS DDR2 SDRAMs in FBGA packages on a 240-

pin glass epoxy substrate.The memory array is designed with Double Data

Rate (DDR2) Synchronous DRAMs for unbuffered applications.

The pipelined, multibanked architecture of DDR2 SDRAMs allows for

concurrent operation, thereby providing high, effective bandwidth.

Decoupling capacitors are mounted on the PCB board in parallel for each

DDR2 SDRAM, which provides proper voltage supply impedance over the

whole frequency range of operations, in accordance with JEDEC

specifications.

These modules feature Serial Presence Detect (SPD) based on a serial

EEPROM device, using the 2-pin I2C protocol.

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takeMS TMS1GB264C08x-805xx Features 240-pin Unbuffered DDR2 SDRAM JEDEC standard 1.8V I/

Technical details - 1024 MB longdimm module - 64Mx8 IC organisation - x64 module organisation - 800MHz / PC2 6400 - double sided / 16 ICs -

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TakeMS TMS1GB264C081-804 Datový list